1. Field of the Invention
The present invention relates to a semiconductor module including a plurality of semiconductor memory devices, and particularly relates to a semiconductor module, which allows the semiconductor memory devices in the module to shift to a test mode for testing a special operation, as well as the semiconductor memory devices used therein.
2. Description of the Background Art
In recent years, attention has been given to a DIMM (Double Inline Memory Module), which operates in synchronization with a clock signal having a frequency of 50 MHz or more. The DIMM has two semiconductor modules formed on the opposite sides of one substrate, respectively. The semiconductor module includes a plurality of DRAMs (Dynamic Random Access Memories).
In particular, the semiconductor module used in a registered DIMM (RDIMM) includes a plurality of DRAMs, a PLL circuit and a registered buffer circuit. The PLL circuit generates a clock signal having a frequency of 50 MHz or more and adjusts timing, according to which various signals and data are applied to the plurality of DRAMs. The registered buffer circuit receives the control signal, data and address signal, which are externally applied, and converts the voltage levels forming the control signals and others to the voltage levels to be used in the semiconductor module for applying them to the plurality of DRAMs.
The DRAMs used in the RDIMM are subjected to a test of an operation within the normal specifications and a test of a special operation not defined by the normal specifications in a production process. By these tests, faulty pieces are detected and removed.
The DRAM includes a test mode circuit shown in FIG. 23. The test mode circuit generates a test mode signal for shifting the DRAM to a test mode, in which the special operation test is performed based on an externally supplied predetermined signal. When the test mode signal is generated, the test of the special operation not defined by the normal specifications is performed in the DRAM.
Referring to FIG. 23, test mode circuit 600 included in the DRAM includes hold circuits 601–603, AND gates 604 and 605, and an SVIH detector 606. Hold circuit 601 holds a signal MRS, which attains H-level (logical high level) when row address strobe signal /RAS, column address strobe signal /CAS and write enable signal /WE are all at L-level (logical low level), for a predetermined period, and then outputs hold signal MRSH to AND gates 604 and 605. Hold circuit 602 holds a bank address signal BA1 for a predetermined period, and then outputs a hold signal BA1H to AND gates 604 and 605. Hold circuit 603 holds an address signal ADD7 for a predetermined period, and then outputs a hold signal ADD7H to AND gates 604 and 605.
AND gate 605 performs logical AND among three hold signals MRSH, BA1H and ADD7H, and outputs a signal SVDENE to an SVIH detector 606. SVIH detector 606 is activated when it receives signal SVDENE of H-level, and makes a comparison between a voltage level of a signal SVIH, which is applied via a pin receiving bank address signal BA0, and a reference voltage level VREF. When the voltage level of bank address signal BA0 is higher than reference voltage level VREF, signal BA0S of H-level is output to AND gate 604. When the voltage level of bank address signal BA0 is lower than reference voltage level VREF, signal BAOS of L-level is output to AND gate 604. AND gate 604 performs the logical AND among hold signals MRSH, BA1H and ADD7H and signal BA0S, and outputs a result thereof as a test mode signal TM.
Referring to FIG. 24, description will now be given on an operation of producing test mode signal TM by test mode circuit 600. For shifting the DRAM to the test mode, the DRAM is supplied with row address strobe signal /RAS of L-level, column address strobe signal /CAS of L-level, write enable signal /WE of L-level, bank address signal BA1 of H-level, address signal ADD7 of H-level and signal SVIH, which is formed of a voltage level higher than the voltage level in a normal operating range. Thereby, hold circuits 601–603 of test mode circuit 600 produce hold signals MRSH, BA1H and ADD7H of H-level for a predetermined period, respectively, and output them to AND gates 604 and 605.
AND gate 605 performs logical AND among three hold signals MRSH, BA1H and ADD7H to produce signal SVDENE of H-level, and sends it to SVIH detector 606. Thereby, SVIH detector 606 is activated to compare the voltage level of signal SVIH with reference voltage level VREF, and issues signal BA0S, which is formed of the logical level corresponding to a result of the comparison, to AND gate 604. For shifting to the test mode, signal SVIH is formed of the voltage level higher than the voltage level in the normal operating range so that SVIH detector 606 outputs signal BA0S at H-level to AND gate 604.
Accordingly, SVIH detector 606 is activated at timing T2 after elapsing of a predetermined period from timing T1, at which hold signals MRSH, BA1H and ADD7H rise to H-level, and it is determined between timing T2 and timing T3 whether the voltage level of signal SVIH is higher than reference voltage level VREF or not.
AND gate 604 performs the logical AND among received hold signals MRSH, BA1H and ADD7H, and signal BA0S, and generates test mode signal TM of H-level.
As described above, test mode circuit 600 generates test mode signal TM after elapsing of a detector activation time, which is required from start of shift to the test mode to activation of SVIH detector 606, and a determination time required for determining whether the voltage level of signal SVIH is higher than reference voltage level VREF or not. Thus, test mode circuit 600 requires a time T for activating the detector and detecting signal SVIH.
The DRAM is shifted to the test mode, and the test of the special operation is performed. DRAMs, in which a failure was detected in the special operation test, are eliminated, and only DRAMs, in which no failure was detected, are assembled into the semiconductor modules to produce the RDIMMs.
The RDIMM thus produced is not subjected to the test of the special operation not defined by the normal specifications, and is subjected only to the test of the operation defined by the normal specifications before shipment.
However, it has been recently required to perform the special operation test in the state of RDIMM, i.e., in the modular state. However, the RDIMM is provided with a registered buffer circuit, which lowers the voltage level of signal SVIH to the voltage level to be used within the module when signal SVIH formed of the voltage level higher than the voltage level in the normal operating range is externally supplied and applies the lowered signal SVIH to the DRAM. Therefore, such a problem occurs that each of the DRAMs in the module cannot be shifted to the test mode for performing the special operation test.
As described above, the test mode circuit mounted on the DRAM is provided with the SVIH detector requiring the detector activation time and the determination time for detecting signal SVIH. Therefore, it is impossible to detect signal SVIH within one cycle of the clock signal having a frequency of 50 MHz or more, at which RDIMM operates, and each DRAM in the module cannot shift to the test mode. Thus, the time T is required for the activating of the detector and the detection of signal SVIH, and this time T cannot be shorter than one cycle of the clock signal so that each DRAM cannot shift to the test mode.